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FInd Below the list of our technical publications in Papers or Conferences:

2006
"Ultra Low-Power 10-bit A/D Converter for Harsh Environments", L. Demeûs, L. Vancaillie, V. Dessard, and G. Picún, HITEC 2006, May 2006, Santa Fe, USA

"A High Temperature A High Temperature Floating Gate MOSFET Driver for on-the-engine Injector Control", V. Dessard, G. Picún, O. Stevens, L. Demeûs, P. Delatte, AMAA 2006, 25-26 April 2006, Berlin, Germany

"A SOI Floating Gate MOSFET Driver for High Temperature Automotive Applications", V. Dessard, G. Picún, O. Stevens, L. Demeûs, P. Delatte, 2nd EUROSOI Workshop 8-10 March 2006, Grenoble, France.


2005
"A Low-Power 5 GHz CMOS LC-VCO Optimized for High-Resistivity SOI Substrates", P. DELATTE, G. PICUN, L. DEMEUS, P. SIMON and D. FLANDRE, ESSCIRC 2005, September 2005, Grenoble, FRANCE  

"High Temperature Analogue Circuits Developed within the European Research Project ATHIS: Advanced Technique for High Temperature System-On-Chip", V. DESSARD, P. DELATTE, G. PICUN, O. STEVENS and L. DEMEUS, HITEN2005, September 2005, Paris, FRANCE

"The ATHIS Project: Advances Techniques for High Temperature System-On-Chip", D. FLANDRE, E. CABRUJA, L. DEMEUS, V. DESSARD, X. JORDA, A. MANZONE, S. RICHTER, So. RICHTER, G. RUSSELL, and J-D LEGAT, HITEN 2005, Spetember 2005, Paris, FRANCE.

"Versatile High Performance Negative Voltage Regulator for High Temperature applications", V. DESSARD, G. PICUN, P. DELATTE and L. DEMEUS, HITEN 2005, Spetembre 2005, Paris, FRANCE.

"CHT-CG-050: Highly Versatile, 3-5V High-Frequency Crystal Clock Generator for High Temperature Applications", G. PICUN, V. DESSARD, P. DELATTE, O. STEVENS and L. DEMEUS, HITEN2005, September 2005, Paris, FRANCE.

"Low Power 80C51 Microcontroller in SOI High Temperature Technology", Ph. MANET, R. Ambroise, D. BOL, L. DEMEUS, and J-D LEGAT, HITEN2005, September 2005, Paris, FRANCE.

"Deep-submicron SOI CMOS mixed-signal circuits for High Temperature Applications?", L. VANCAILLIE, D. LEVACQ, V. KILCHYTSKA and D. FLANDRE, HITEN2005, Paris, FRANCE.

“Optimization of Spiral Inductors on High-resistivity SOI Substrates for Low-power LC-VCO Design”, P. DELATTE, L. DEMEUS, P. SIMON, D. FLANDRE, EUROSOI Workshop, January 2005, (Granada, Spain)

2004

“Small- and Large-Signal RF Characterization of Fully-Depleted Accumulation-mode Varactors for Low-Voltage LC-VCO SOI Design”, B. PARVAIS, P. DELATTE, H. MATSUHASHI, F. ICHIKAWA, P. SIMON, D. SCHREURS, D. FLANDRE and J.-P. RASKIN, IEEE SOI Conference, October 2004 (Charleston)

“SOI-optimized RF Design”, P.  DELATTE, Medea+ 4GRadio Workshop on SOI Technology for RF Application, October 2004, Louvain-la-Neuve (Belgium)

“Noise modeling and performance in 0.15-µm fully depleted SOI MOSFET”, G. PAILLONCY, B. INIGUEZ, G. DAMBRINE, M. DEHAN, J. RASKIN, H. MATSUHASHI, P. DELATTE, F. DANNEVILLE, , to be presented at the SPIE Conference on Fluctuation & Noise, May 2004, Maspalomas, (Gran Canaria, Spain)

“High Temperature SOI Voltage Reference, Voltage Regulator and Xtal Oscillator Driver Specified up to 225°C and Functional above 300°C”, V. DESSARD, G. PICUN, P. DELATTE, L. DEMEUS, HITEC Conference, May 2004, (Santa Fe, NM, USA)

“High Temperature SOI Voltage Reference, Voltage Regulator and Xtal Oscillator Driver Specified up to 225°C and Functional Above 300°C.”, V. DESSARD, G. PICUN, P. DELATTE, L. DEMEUS, HITEC Conference, May 2004, (Santa Fe, NM, USA)

"Recent advances in SOI MOSFETs devices and circuits for ultra-low power / high temperature applications", D. LEVACQ, V. DESSARD and D. FLANDRE, Conf. Abstracts of NATO Advanced Research Workshop, Science and Technology of SOI Structures and Devices Operating in Harsh Environment, pp.41-42, April 25-29, 2004, (Kyiv, Ukraine)

“Low-noise silicon-on-insulator hall devices”, Y. HADDAB, V. MOSSER, M. LYSOWEC, J. SUSKI, L. DEMEUS, C. RENAUX, S. ADRIEAENSEN, D. FLANDRE, Fluctuation and Noise Letters [An Interdisciplinary Scientific Journal on Random Processes in Physical, Biological and Technological Systems], Vol. 4, No. 2 (2004) L345-L354.

"Composite ULP diode fabrication, modeling and applications in multi-Vth FD SOI CMOS technology", D. LEVACQ, C. LIBER, V. DESSARD and D. FLANDRE, Solid State Electronics, vol. 48/6, pp. 1017-1025, 2004.

2003

 “Peculiarities of the temperature behavior of SOI MOSFETs in the deep submicron area”, L. VANCAILLIE, V. KYLCHYTSKA, P. DELATTE, L. DEMEUS, H. MATSUHASHI, F. ICHIKAWA and D. FLANDRE, IEEE SOI Conference, October 2003 (Newport Beach, California)

“Why all the buzz about SOI?”, D. CORSON & P. DELATTE, in RF Design, October 2003

"Ultra Low-Power design techniques using special SOI MOS diodes", D. LEVACQ, C. LIBER, V. DESSARD and D. FLANDRE, 2003 IEEE International SOI Conference, September 29-October 2, 2003 (Newport Beach, USA)

"Conception de circuits analogiques micro-puissance en technologie CMOS-SOI", D. LEVACQ, S. ADRIEAENSEN, C. LIBER, V. DESSARD and D. FLANDRE, Colloque TAISA'2003, 25-26 septembre 2003, Louvain-la-Neuve (Belgique)

“0.15µm Fully Depleted SOI for Mixed-Signal Applications up to 250°C: Are We Approaching the Limits of Device Scaling for High-Temperature Electronics?”, L. VANCAILLIE, V. KYLCHYTSKA, P. DELATTE, H. MATSUHASHI, F. ICHIKAWA and D. FLANDRE, in 2003 HITEN Conference, July 8-10 2003, (Oxford, UK)

“On the potential of 0.2µm Fully-Depleted SOI for low-power Mixed and Digital Circuits for applications up to 225°C”, P. DELATTE, L. DEMEUS, L. VANCAILLIE, V. KYLCHYTSKA, Y. KAWAI , F. ICHIKAWA and D. FLANDRE, in 2003 HITEN Conference, July 8-10 2003 (Oxford, UK)

"A Novel CMOS Memory Cell Architecture for Ultra-Low Power Applications operating up to 280°C", D. LEVACQ, V. DESSARD, D. FLANDRE, 203rd meeting of the Electrochemical Society, April 22- May 7, 2003, (Paris, France)

“Low-noise SOI Hall devices”, Y. HADDAB, V. MOSSER, M. LYSOWEC,  J. SUSKI, L. DEMEUS, Ch. RENAUX, S. ADRIEAENSEN, D. FLANDRE, Noise and Information in Nanoelectronics, Sensors, and Standards. Edited by Kish, Laszlo B.; Green, Frederick; Iannaccone, Giuseppe; Vig, John R. Proceedings of the SPIE, Volume 5115, pp. 196-203 (2003), March 2003

“Peculiarities of the temperature behavior of SOI MOSFETs in the deep submicron area”, L. VANCAILLIE, V. KYLCHYTSKA, P. DELATTE, L. DEMEUS, H. MATSUHASHI, F. ICHIKAWA and D. FLANDRE, International SOI Conference 2003, ********, (USA)

“Versatile high performance Voltage Regulator for high temperature applications”, V. DESSARD, G. PICUN, P. DELATTE and L. DEMEUS, HITEN Conference 2003, (Oxford, UK)

“On the Potential 0.2 µm Fully-Depleted SOI for Low-power Mixed and Digital Circuits for Applications up to 225°C”, P. DELATTE, G. PICUN, L. DEMEUS, L. VANCAILLIE, V. KYLCHYTSKA, D. FLANDRE, Y. KAWAI and F. ICHIKAWA, HITEN Conference 2003, (Oxford, UK)
2002

“SOI Analog Design for Low Power and High-temperature Applications”, P. DELATTE, SOITEC Workshop (Invited Paper), September 2002, (Sainte-Maxime, France)

"25 to 300°C ultra-low-power voltage reference compatible with standard SOI CMOS process", S. ADRIEAENSEN, V. DESSARD and D. FLANDRE, Electronics Letters, Vol. 38, No. 19, pp. 1103-1104, September 2002

“Intelligent SOI CMOS Integrated Circuits and Sensors for Heterogeneous Environments and Applications”, D. FLANDRE, S. ADRIEAENSEN, A. AFZALIAN, J. LACONTE, D. LEVACQ, C. RENAUX, L. VANCAILLIE and J.-P. RASKIN L. DEMEUS, P. DELATTE, V. DESSARD, G. PICUN, 2002, IEEE Sensors 2002, June 12-14 2002, (Orlando, FL, USA)

“A Voltage Reference Compatible with Standard SOI CMOS Processes and Consuming 1pA to 50nA from room temperature up to 300°C”, S. ADRIEAENSEN, V. DESSARD, D. FLANDRE, International SOI Conference 2002, *****

“SOI solutions for automotive applications”, L. DEMEUS, P. DELATTE, G. PICUN, V. DESSARD and Pr. D. FLANDRE, AMAA Conference 2002, (Berlin, Germany)

“Electrical characterization of an industrial SOS-CMOS process up to 300°C.”, L. VANCAILLIE, V. KYLCHYTSKA, D. LEVACQ, V. DESSARD, L. DEMEUS  and  D. FLANDRE, HITEC Conference 2002, *****

"Intelligent SOI CMOS integrated circuits and sensors for heterogeneous environments and applications", D. FLANDRE, S. ADRIEAENSEN, A. AFZALIAN, L. DEMEUS, P. DELATTE, J. LACONTE, D. LEVACQ, C. RENAUX, V. DESSARD, G. PICUN, L. VANCAILLIE, J.-P. RASKIN, Proceedings of IEEE Sensors 2002, Volume 2, pp. 1407-1412, 2002.

2001

“SOI n-MOSFET low-frequency noise from full to partial depletion: measurements, modeling and implications for analog designs”, V. DESSARD, S. ADRIAENSEN, D. FLANDRE, Proceedings of the IEEE 2001 International SOI Conference, 2-4 October 2001, (Durango, CO - USA)

“Comparison of Bulk vs. SOI for low power low voltage CMOS imager”, A. AFZALIAN, P. DELATTE, J.-D. LEGAT, D. FLANDRE, IEEE SOI conference October 2001, (Durango, CO - USA)

“Deep-Submicron DC to RF SOI MOSFET Macro-Model”,  B. IÑÍGUEZ, J. P. RASKIN, L. DEMEUS, A. NEVE, D. VANHOENACKER, P. SIMON , and D. FLANDRE IEEE Trans on Electron Devices, vol. 48, no. 9, pp. 1981-1988, September 2001

“Bulk vs SOI CMOS APS optimal design for low power low voltage applications”, A. AFZALIAN, P. DELATTE, J.-D. LEGAT, D. FLANDRE, In: ECCTD'01 - European Conference on Circuit Theory and Design, August 28-31, 2001, 2001, p. pp. II-53 - II-56, Espoo (Finland)

“Ultra-Low Power High-Temperature Voltage Reference Using Standard SOI CMOS Process”, V. DESSARD, S. ADRIEAENSEN, D. FLANDRE, HITEN'2001 - International Conference on High Temperature Electronics, p. 163-165, June 5-8, 2001, Oslo (Norway)

“High Temperature Characterization of Carrier Generation in SOI MOS Devices Using Gated-Diode Technique”, T. RUDENKO, V. KYLCHYTSKA, D. FLANDRE, V. DESSARD, HITEN'2001 - International Conference on High Temperature Electronics, p. 81-88, June 5-8, 2001, 2001, Oslo (Norway)

“Analysis and Potential of the Bipolar- and Hybrid-Mode Thin-Film SOI MOSFETs for High-Temperature Applications”, S. ADRIEAENSEN, V. DESSARD, D. FLANDRE, HITEN'2001 - International Conference on High Temperature Electronic, 2001, p. pp. 74-78, June 5-8, 2001, Oslo (Norway)

“Status and Perspectives of SOI-Technologies and -Applications”, P. DELATTE, L. DEMEUS, V. DESSARD, G. PICUN, D. FLANDRE, In: From BULK to SOI: A designer point of view, 17-18 May, 2001, Munich (Germany)
“From BULK to SOI: a designer point-of-view”, P. DELATTE, L. DEMEUS, V. DESSARD, G. PICUN, D. FLANDRE, VDE/VDI GLL Workshop on “Stand un Perspektiven von SOI-Techologien un Anwendungen”, (Invited Paper), May 2001, München (Deutschland)

“A new fully-depleted SOI MOSFET macro-model valid from DC to RF”, B. INIGUEZ, J.-P. RASKIN, L. DEMEUS, A. NEVE DE MEVERGNIES, M. GOFFIOUL, P. SIMON, D. VANHOENACKER, D. FLANDRE, Proceedings of the 10th International Symposium on SOI Technology and Devices, ECS Meeting, Electrochemical Society Proceedings, p. pp. 193-198. 25-29 March, 2001, (Washington)

“Improvement of sub-0.25 µm fully-depleted SOI CMOS analog performance by thinning the SI film”, A. NEVE DE MEVERGNIES, V. DESSARD, P. DELATTE, V. BRODEOUX, B. INIGUEZ, E. RAULY, D. FLANDRE, In: Proceeding of the 10th International Symposium SOI Technology and Devices, ECS Meeting, The Electrochemical Society, 2001, Electrochemical Society Proceedings, p. pp. 271-276, 25-29 March 2001, (Washington)

“Charge injection characterization of thin-film SOI MOS transistors at high temperature”, G. PICUN, L. DEMEUS, D. FLANDRE, In: Silicon-on-insulator technology and devices X. Proceedings of the Tenth International Symposium, The Electrochemical Society, Inc., 2001, Proceedings, p. pp. 115-120, 25-29 March 2001, Pennington (USA)

“A New Fully-Depleted SOI MOSFET Macro-Model Valid from DC to RF”, B. INIGUEZ, J.-P. RASKIN, L. DEMEUS, A. NEVE, M. GOFFIOUL, P. SIMON, D. VANHOENACKER and D. FLANDRE Proc. of the 10th International Symposium on Silicon-on-Insulator Technology and Devices, 199th Electrochemical Society Meeting, 03/2001, Washington DC (USA)

“Improvement of sub-0.25 mm Fully-Depleted SOI CMOS Analog Performance by Thinning the Si Film”, V. DESSARD, B. INIGUEZ,V. BRODEOUX, A. NEVE,E. RAULY and D. FLANDRE Proc. of the 10th International Symposium on Silicon-on-Insulator Technology and Devices, 199th Electrochemical Society Meeting, 03/2001, Washington DC (USA)

“Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower”, High-Temperature or RF Microsystems, J.-P. RASKIN, J. LACONTE, A. AKHEYAR, C. DUPONT, S. ADRIEAENSEN, A. NEVE, M. DEHAN, B. PARVAIS, D. VANHOENACKER, L. DEMEUS, P. DELATTE, V. DESSARD, D. FLANDRE, HF JOURNAL, 2/2001

“Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems, Solid-State Electronics”, D. FLANDRE, S. ADRIEAENSEN, A. AKHEYAR, A. CRAHAY, L. DEMEUS, P. DELATTE, V. DESSARD, B. INIGUEZ, A. NEVE DE MEVERGNIES, B. KATSCHMARSKYJ, P. LOUMAYE, J. LACONTE, I. MARTINEZ, G. PICUN, E. RAULY, C. RENAUX, D. SPOTE, M. ZITOUT, M. DEHAN, B. PARVAIS, P. SIMON, D. VANHOENACKER, J.-P. RASKIN, 45, p. 541-549, 2001

“Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems”, J.-P. RASKIN, J. LACONTE, A. AKHEYAR, S. ADRIEAENSEN, A. NEVE, I. MARTINEZ, M. DEHAN, B. PARVAIS, D. VANHOENACKER-JANVIER, L. DEMEUS, P. DELATTE, D. FLANDRE, Belgian Journal of Electronics & Communications (Revue HF), ((2)), p. p. 53-68, 2001

 “Deep-Submicrometer DC-to-RF SOI MOSFET Macro-Model”, B. INIGUEZ, J.-P. RASKIN, L. DEMEUS, A. NEVE DE MÉVERGNIES, D. VANHOENACKER, P. SIMON, M. GOFFIOUL, D. FLANDRE, IEEE transactions on electron devices, 48, p. 1981-1988, (9), 2001

“Fully depleted SOI CMOS technology for heterogeneous micropower”, D. FLANDRE, S. ADRIEAENSEN, A. AKHEYAR, A. CRAHAY, L. DEMEUS, P. DELATTE, V. DESSARD, B. INIGUEZ, A. NEVE DE MEVERGNIES, B. KATSCHMARSKYJ, P. LOUMAYE, J. LACONTE, I. MARTINEZ, G. PICUN, E. RAULY, C. RENAUX, D. SPOTE, M. ZITOUT, M. DEHAN, B. PARVAIS, P. SIMON, D. VANHOENACKER, J.-P. RASKIN, high-temperature or RF microsystems, Solid-State Electronics, 45, p. 541-549, 2001

<2000

“Innovative SOI circuit design for extreme applications”, L. DEMEUS, P. DELATTE, V. DESSARD, D. FLANDRE, In: Proc. of EUROSOI'2000, European Meeting on Silicon on Insulator Devices, 2000, p. 4 pp, October 25-27, 2000, Granada (Spain)

“Comparison of 0.25 micron Bulk, PD and FD SOI CMOS implementations of a Low-Voltage Low-Power Programmable DLL for Linear Delay Generation”, P. DELATTE, V. BRODEOUX, P. LORENT, D. FLANDRE, In: Proc. of the 2000 IEEE International SOI Conference, p. 92 to 93, October 2-5, 2000, Wakefield (USA)

“Characterization, modeling and simulation of a PLL under characterization using HDL-A”, I. MARTINEZ, P. DELATTE, D. FLANDRE, Proceedings of the IEEE/ACM international workshop on Behavioral modeling and simulation, October 2000, (Orlando)

“Characterization and high-level modeling of SOI ring oscillators under irradiation”, I. MARTINEZ, P. DELATTE, G. BERGER, D. FLANDRE, In: Proc. of "Les journées techniques du RADECS'2000", 2000, p. 205 to 208, September 11-13, 2000, Louvain-la-Neuve (Belgium)

"Review of fully-depleted SOI CMOS technology for Microsystems”, L. DEMEUS, P. DELATTE, V. DESSARD, S. ADRIEAENSEN, C. RENAUX, D. FLANDRE, , In: Proceedings of the 3rd Int. Conf. on Micro Materials, B. MICHEL, T. WINKLER, M. WERNER and H. FECHT ed(s), Verlag, ISBN : 3-932434-15-3, p. 357-362 (Invited Paper), 2000, (Dresden)
 
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